1. Field of the Invention
The present invention relates to frequency synthesis, and particularly, but not exclusively, to frequency-locked loops.
2. Description of the Related Art
Frequency-locked loops (FLLS) are blocks that perform the function shown in FIG. 1. That is, an input signal at a fixed first frequency Fin is supplied to a FLL 10, and the FLL 10 outputs a signal at a fixed second frequency Fout that is not equal to Fin. This general principle is known as frequency synthesis.
FIG. 2 shows an implementation of a FLL 20. A signal is input to an integrator 22, which outputs a signal to a voltage-controlled oscillator 24 (VCO). The frequency of the output signal from the VCO 24 is controlled by its input signal. A high input signal into the VCO 24 leads to a high-frequency output signal from the VCO 24, and a low input signal into the VCO 24 leads to a low-frequency output signal from the VCO 24. The signal output Fout from the VCO 24 is sampled, its frequency divided by a factor N in a ÷N block 26, and the resulting output frequency signal Fout/N is fed back to be subtracted from the input signal Fin in a subtracting element 27. The difference ΔF between the frequency of the input signal Fin and the feedback signal Fout/N is calculated and fed back into the loop. In this way, the system converges to an output signal with a frequency of Fout=N×Fin.
It is of course desirable for the system to be able to synthesize an output frequency Fout which is not an integer multiple of the input frequency Fin. That is, N need not necessarily be an integer. However, dividing by a fractional number is difficult.
It is advantageous to realize as much of the FLL as possible using digital circuitry, due to the benefits that are inherent with digital signal processing (i.e. cheaper, smaller die area, rapid testability, etc).